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september 2006 rev 2 1/44 44 ST7540 fsk power line transceiver general features half-duplex frequency shift keying (fsk) transceiver integrated power line driver with programmable voltage and current control programmable mains access: ? synchronous ? asynchronous single supply voltage (from 7.5v up to 13.5v) very low power consumption (i q = 5ma) integrates 5v voltage regulator (up to 50ma) with short circuit protection integrated 3.3v voltage regulator (up to 50ma) with short circuit protection 3.3v or 5v digital supply 8 programmable transmission frequencies programmable baud rate up to 4800bps receiving sensitivity up to 250 v rms suitable for applications in accordance with en 50065 cenelec specification carrier or preamble detection band in use detection programmable control register watchdog timer 8 or 16 bit header recognition st7537 and st7538 compatible uart/spi host interface description the ST7540 is a half duplex synchronous/asynchronous fsk modem designed for power line communication network applications. it operates from a single supply voltage and integrates a line driver and two linear regulators for 5v and 3.3v. the device operation is controlled by means of an internal register, programmable through the synchronous serial interface. additional func tions as watchdog, clock output, output voltage and current control, preamble detection, time-out and band in use are included. realized in multipower bcd5 technology that allows to integrate dmos, bipolar and cmos structures in the same chip. htssop28 exposed pad www.st.com order codes part number package packaging ST7540 htssop28 (exposed pad) tube ST7540tr htssop28 (exposed pad) tape and reel
contents ST7540 2/44 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 crystal resonator and external clock . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 carrier frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.3 mark and space frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.4 ST7540 mains access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.5 host processor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.5.1 communication between host and ST7540 . . . . . . . . . . . . . . . . . . . . . 20 6.5.2 control register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.6 receiving mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.7 transmission mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.8 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
ST7540 contents 3/44 7 auxiliary analog and digital functions . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 band in use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2 time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.3 reset & watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.4 output clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.5 output voltage level freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.6 extended control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.7 under voltage lock out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.8 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.9 5v voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.10 3.3v voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.11 power-up procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
block diagram ST7540 4/44 1 block diagram figure 1. block diagram

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ST7540 pin settings 5/44 2 pin settings 2.1 pin connection figure 2. pin connection (top view) 2.2 pin description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 cd_pd reg_data gnd rxd rxtx txd bu/therm clr/t v dd mclk rsto uart/spi wd pa_in- test2 test1 vdc rx_in cl vsense x2 x1_oscin sv ss tx_out pa_in+ v cc v ss pa_out table 1. pin description n name type description 1 cd_pd digital/output carrier, preamble or frame header detect output. "1" no carrier, preamble or frame header detected "0" carrier, preamble or frame header detected 2reg_data digital/input with internal pull-down mains or control register access selector "1" - control register access "0" - mains access 3 gnd supply digital ground 4 rxd digital/output rx data output. 5 rxtx digital/input with internal pull-up rx or tx mode selection input. "1" - rx session "0" - tx session 6txd digital/input with internal pull-down tx data input.
pin settings ST7540 6/44 7 bu/therm digital/output band in use/thermal shutdown event detection output. in rx mode: "1" signal within the programmed band "0" no signal within the programmed band in tx mode: "1" - thermal shutdown event occurred "0" - no thermal shut down event occurred (signal not latched) 8 clr/t digital/output synchronous mains access clock or control register access clock 9 v dd supply/power digital supply voltage or 3.3v voltage regulator output 10 mclk digital/output master clock output 11 rsto digital/output power on or watchdog reset output 12 uart/spi digital/input with internal pull-down interface type: ?0? - serial peripheral interface ?1? - uart interface 13 wd digital/input with internal pull-up watchdog input. the internal watchdog counter is cleared on the falling edges. 14 pa_in- analog/input power line amplifier inverting input 15 pa_out power/output power line amplifier output 16 v ss supply power analog ground 17 v cc supply power supply voltage 18 pa_in+ analog/input power line amplifier not inverting input 19 tx_out analog/output small signal analog transmit output 20 sv ss supply analog signal ground 21 x1 analog/output crystal oscillator output 22 x2 analog/input crystal oscillator input - or external clock input 23 v sense (1) analog/input output voltage sensing input for the voltage control loop 24 cl (2) analog/input current limiting feedback. a resistor between cl and sv ss sets the pli current limiting value. an integrat ed 80pf filtering input capacitance is present on this pin. 25 rx_in analog/input receiving analog input 26 vdc power 5v voltage regulator output 27 test1 digital/input with internal pull-down test input. must be connected to gnd. 28 test2 analog/input test input. must be connected sv ss 1. cannot be left floating 2. cannot be left floating table 1. pin description (continued) n name type description
ST7540 electrical data 7/44 3 electrical data 3.1 maximum ratings 3.2 thermal data table 2. absolute maximum ratings symbol parameter value unit v cc power supply voltage -0.3 to + 14 v v dd digital supply voltage -0.3 to +5.5 v sv ss /gnd voltage between sv ss and gnd -0.3 to +0.3 v v i digital input voltage gnd - 0.3 to v dd +0.3 v v o digital output voltage gnd - 0.3 to v dd +0.3 v i o digital output current -2 to +2 ma v sense , x2,pa_in- ,pa_in+, cl voltage range at vsense, x2, pa_in-, pa_in+, cl inputs sv ss - 0.3 to 5.6 v rx_in voltage range at rx_in input -5.6 to 5.6 v tx_out, x1 voltage range at tx_out, x1 outputs sv ss - 0.3 to 5.6 v pa_out voltage range at powered pa_out output v ss - 0.3 to +v cc +0.3 v i(pa_out) power line driver output current (1) 1. this current is intended as not repetitive pulse current 650 marms t a operating ambient temperature -40 to +85 c t stg storage temperature -50 to 150 c rxd, pa _ o u t p i n maximum withstanding voltage range test condition: cdf-aec-q100-002- ?human body model? acceptance criteria: ?normal performance? 1750 v other pins 2000 v table 3. thermal data symbol parameter htssop28 exposed pad unit r thja1 maximum thermal resistance junction-ambient steady state (1) 1. mounted on multilayer pcb with a dissi pating surface on the bottom side of the pcb 35 c/w r thja2 maximum thermal resistance junction-ambient steady state (2) 2. it is the same condition of the point above, without any heatsinking surface on the board. 70 c/w
electrical data ST7540 8/44 3.3 recommended operating conditions table 4. recommended operating conditions symbol parameter test condition value unit v cc max allowed slope during power-up 100 v/ms i(v cc ) powered analog supply current with digital supply provided externally maximum total current 650 marms v cc - v dd maximum voltage difference between v cc and vdd during power-up sequence v dd < 4.75v with 5v digital supply provided externally 1.2 v v pa _ o u t output voltage swing for pa_out pin v cc -4.5 v pp i(pa_out) maximum output transmitting current in programmable current limiting r cl = 1.4k ? ; r load =1 ? (as in figure 17 ) 500 marms
ST7540 electrical characteristics 9/44 4 electrical characteristics table 5. electrical characteristics ( v dd = +5v, v cc =+9 v, v ss = s v ss = gnd = 0v,-40c t a 85c, t j < 125c, unless otherwise specified) symbol parameter test condition min. typ. max. unit v dd digital supply voltages 5v digital supply provided externally 4.75 5 5.25 v v cc power supply voltage 7.5 13.5 v i(v dd ) digital input supply current transmission & receiving mode (mclk = 4mhz),no load 3.5 ma transmission & receiving mode (mclk = off), no load 1.5 ma i(v cc ) power supply current current with digital supply provided externally tx mode, no load 60 marms rx mode 5 marms uvlo under voltage lock out threshold on v cc 3.7 3.9 4.1 v uvlo hys uvlo hysteresis on v cc 340 mv digital i/o r down internal pull down resistor -30% 100 +30% k ? r up internal pull up resistor -30% 100 +30% k ? digital i/o - 5v digital supply v ih high logic level input voltage 2 v v il low logic level input voltage 1.2 v v oh high logic level output voltage i oh = -2ma v dd - 0.45 v v ol low logic level output voltage i ol = 2ma gnd + 0.3 v digital i/o - 3.3v digital supply v ih high logic level input voltage 1.4 v v il low logic level input voltage 0.8 v
electrical characteristics ST7540 10/44 v oh high logic level output voltage i oh = -2ma v dd - 0.75 v v ol low logic level output voltage i ol = 2ma gnd + 0.4 v oscillator external clock x2 voltage swing external clock. figure 4 5 v pp external clock x2 dc voltage level external clock. figure 4 2.5 v dc xtal clock duty cycle external clock. 40 60 % xtal crystal oscillator frequency fundamental 16 mhz xtal esr external oscillator esr resistance 40 ? xtal cl external oscillator stabilization capacitance figure 6 16 pf transmitter i tx_out output transmitting current on tx_out 1marms v tx_out max carrier output ac voltage r cl = 1.4k ? vsense = 0v 1.75 2.3 3.5 v pp v tx_outdc output dc voltage on tx_out 1.7 2.1 2.5 v hd2 tx_out second harmonic distortion on tx_out v tx_out = 2v pp ; fc = 86khz, no load -42 db c hd3 tx_out third harmonic distortion on tx_out v tx_out = 2v pp ; fc = 86khz, no load -49 db c g accuracy accuracy on voltage control loop active r cl = 0 ? -1 +1 gst g st alc gain step control loop gain step 0.6 1 1.4 db drng alc dynamic range 30 db c cl input capacitance on cl pin 80 pf v senseth voltage control loop reference threshold on v sense pin figure 17 160 180 200 mv pk v sensehyst hysteresis on voltage loop reference threshold figure 17 18 mv table 5. electrical characteristics (continued) ( v dd = +5v, v cc =+9 v, v ss = s v ss = gnd = 0v,-40c t a 85c, t j < 125c, unless otherwise specified) symbol parameter test condition min. typ. max. unit
ST7540 electrical characteristics 11/44 v sense v sense input impedance 36 k ? cl th current control loop reference threshold on cl pin figure 17 1.80 1.90 2.00 v cl hyst hysteresis on current loop reference threshold figure 17 210 250 290 mv t rxtx carrier activation time figure 21 - 600 baud xtal = 16mhz 1.6 ms figure 21 - 1200 baud xtal = 16mhz 800 s figure 21 - 2400 baud xtal = 16mhz 400 s figure 21 - 4800 baud xtal = 16mhz 200 s t alc carrier stabilization time from step 16 to zero or from step 16 to step 31, figure 21 xtal = 16mhz 3.2 ms t st tstep figure 21 xtal = 16mhz 200 s power amplifier pa in(offset) input terminals offset 18 mv gbwp gain bandwidth product 100 mhz r in input resistance at pa_in+ and pa_in- pins pa_in+ vs. vss (1) 1 m ? pa_in- vs. vss (1) 1 m ? c in input capacitance at pa_in+ and pa_in- pins pa_in+ vs. vss (1) 5pf pa_in- vs. vss (1) 5pf cmrr common mode rejection ratio 40 db table 5. electrical characteristics (continued) ( v dd = +5v, v cc =+9 v, v ss = s v ss = gnd = 0v,-40c t a 85c, t j < 125c, unless otherwise specified) symbol parameter test condition min. typ. max. unit
electrical characteristics ST7540 12/44 hd2 pa _ o u t second harmonic distortion on pa_out v pa _ o u t = 5.6v pp , v cc = 12v r load = 30 ? carrier frequency: 86khz figure 3 -63 db c hd3 pa _ o u t third harmonic distortion on pa_out pin v pa _ o u t = 5.6v pp , v cc = 12v r load = 30 ? carrier frequency: 86khz figure 3 - 63 db c receiver v in input sensitivity (normal mode) 0.5 2 mv rms input sensitivity (high sens.) 250 v rms input sensitivity (txd line forced to ?1?) v bu db/ vrms v in maximum input signal 2 v rms r in input impedance 80 100 140 k ? v cd carrier detection sensitivity (normal mode) 0.5 2 mv rms carrier detection sensitivity (high sensitivity mode) 250 v rms carrier detection sensitivity (txd forced to ?1?) v bu db/ vrms v bu band in use detection level 83.5 86 db/ vrms table 5. electrical characteristics (continued) ( v dd = +5v, v cc =+9 v, v ss = s v ss = gnd = 0v,-40c t a 85c, t j < 125c, unless otherwise specified) symbol parameter test condition min. typ. max. unit
ST7540 electrical characteristics 13/44 5v voltage regulator vdc linear regulator output voltage 0 < io < 50ma 7.5v < v cc < 13.5v -5% 5.05 +5% v 3.3v voltage regulator v dd linear regulator output voltage 0 < io < 50ma 7.5v < v cc < 13.5v -5% 3.3 +5% v other functions t rsto reset time see figure 23 ; xtal = 16mhz 50 ms t wd watch-dog pulse width see figure 23 125 ns t wm watch-dog pulse period minimum value. see figure 23 250 ns maximum value. see figure 23 1490 ms t wo watch-dog time out see figure 23 1.5 s t out tx time out control register bit 7 and bit 8 1 3 s t off time out off time figure 22 125 ms t offd rxtx 0->1 vs. time out delay figure 22 20 s t cd carrier detection time selectable by register control register bit 9 and bit10 figure 14 500 1 3 5 s ms ms ms t dcd cd_pd propagation delay figure 14 300 500 s m clk master clock output selectable by register control register bit 15 and bit 16 see ta b l e 1 2 fclock fclock/2 fclock/4 off mhz baud baud rate control register bit 3 and bit 4 see ta b l e 1 2 600 1200 2400 4800 baud table 5. electrical characteristics (continued) ( v dd = +5v, v cc =+9 v, v ss = s v ss = gnd = 0v,-40c t a 85c, t j < 125c, unless otherwise specified) symbol parameter test condition min. typ. max. unit
electrical characteristics ST7540 14/44 figure 3. pli configuration for pa_out distortions measurement serial interface t b baud rate bit time (1/baud) control register bit 3 and bit 4 (see figure 13 ) 1667 833 417 208 s ts setup time see figures 8, 9, 10, 11 & 12 5ns t h hold time see figures 8, 9, 10, 11 & 12 2ns t cr clr/t vs. reg_data or rxtx see figures 8, 9, 10, 11 & 12 t b /4 t cc clr/t vs. clr/t see figures 8, 9, 10, 11 & 12 t b 2*t b t ds setup time see figures 8, 9, 10, 11 & 12 t b /4 t b /2 t dh hold time see figures 8, 9, 10, 11 & 12 t b /4 t b /2 t crp t h t b /2 1. not tested, guaranteed by design table 5. electrical characteristics (continued) ( v dd = +5v, v cc =+9 v, v ss = s v ss = gnd = 0v,-40c t a 85c, t j < 125c, unless otherwise specified) symbol parameter test condition min. typ. max. unit vcc 10 k ? 2.7 k ? 5 k ? 150 pf 100 pf 1uf 30 ? pa pa_out pa_in - pa_in + measurement point vss v ac = 2vpp v dc = 1.9 v d03in142 6
ST7540 crystal resonator and external clock 15/44 5 crystal resonator and external clock figure 4. external clock waveform figure 5. crystal resonator # $ %&'
&( ) # $ %&'
&( ) x1 x2 d03in1425a 32 pf 32 pf
functional description ST7540 16/44 6 functional description 6.1 carrier frequencies ST7540 is a multi frequency device: eight programmable carrier frequencies are available (see ta b l e 6 ). only one carrier can be used a time. the communication channel could be varied during the normal working mode to realize a multi frequency communication. selecting the desired frequency in the control register the transmission and reception filters are accordingly tuned. 6.2 baud rates ST7540 is a multi baud rate device: four baud rate are available (see ta b l e 8 ). table 6. channels list fcarrier f (khz) f0 60 f1 66 f2 72 f3 76 f4 82.05 f5 86 f6 110 f7 (1) 1. default value 132.5 table 7. ST7540 mark and space tones frequency distance vs. baud rate and deviation baud rate [baud] ? f (1) (hz) 1. frequency deviation deviation (2) 2. deviation = ? f / (baud rate) 600 600 1 (3) 3. deviation 0.5 not allowed 1200 600 1200 0.5 1 2400 (4) 1200 (4) 2400 4. default value 0.5 1 4800 2400 4800 0.5 1
ST7540 functional description 17/44 6.3 mark and space frequencies mark and space communication frequencies are defined by the following formula: f ("0") = fcarrier + [ ? f]/2 f ("1") = fcarrier - [ ? f]/2 ? f is the frequency deviation. with deviation = ?0.5? the difference in terms of frequency between the mark and space tones is half the baudrate value ( ? f=0.5*baudrate). when the deviation = ?1? the difference is the baudrate itself ( ? f= baudrate). the minimal frequency deviation is 600hz. table 8. ST7540 synthesized frequencies carrier frequency (khz) baud rate deviation exact frequency [hz] (clock=16mhz) carrier frequency (khz) baud rate deviation exact frequency [hz] (clock=16mhz) ?1? ?0? ?1? ?0? 60 600 -- 82.05 600 -- 1 59733 60221 1 81706 82357 1200 0.5 59733 60221 1200 0.5 81706 82357 1 59408 60547 1 81380 82682 2400 0.5 59408 60547 2400 0.5 81380 82682 1 58757 61198 1 80892 83171 4800 0.5 58757 61198 4800 0.5 80892 83171 1 57617 62337 1 79590 84473 66 600 -- 86 600 -- 1 65755 66243 1 85775 86263 1200 0.5 65755 66243 1200 0.5 85775 86263 1 65430 66569 1 85449 86589 2400 0.5 65430 66569 2400 0.5 85449 86589 1 64779 67220 1 84798 87240 4800 0.5 64779 67220 4800 0.5 84798 87240 1 63639 68359 1 83659 88379 72 600 -- 110 600 -- 1 71777 72266 1 109701 110352 1200 0.5 71777 72266 1200 0.5 109701 110352 1 71452 72591 1 109375 110677 2400 0.5 71452 72591 2400 0.5 109375 110677 1 70801 73242 1 108724 111165 4800 0.5 70801 73242 4800 0.5 108724 111165 1 69661 74382 1 107585 112467
functional description ST7540 18/44 6.4 ST7540 mains access ST7540 can access the mains in two different ways: synchronous access asynchronous access the choice between the two types of access can be performed by means of control register bit 14(see ta b l e 1 2 ) and affects the ST7540 data flow in transmission mode as in reception mode (for how to set the communication mode, see section 6.5 ). in data transmission mode: synchronous mains access: on clock signal provided by ST7540 (clr/t line) rising edge, data transmission line (txd line) value is read and sent to the fsk modulator. ST7540 manages the transmission timing according to the baudrate selected. asynchronous mains access: data transmission line (txd line) value enters directly to the fsk modulator. the host controller manages the transmission timing (clr/t line should be neglected). in data reception mode: synchronous mains access: on clock signal recovered by a pll from ST7540 (clr/t line) rising edge, value on fsk demodulator is read and put to the data reception line (rxd line). ST7540 recovers the bit timing timing according to the baudrate selected. asynchronous mains access: value on fsk demodulator is sent directly to the data reception line (rxd line). the host controller recovers the communication timing (clr/t line should be neglected). 76 600 -- 132.5 600 -- 1 75684 76335 1 132161 132813 1200 0.5 75684 76335 1200 0.5 132161 132813 1 75358 76660 1 131836 133138 2400 0.5 75358 76660 2400 0.5 131836 133138 1 74870 77148 1 131348 133626 4800 0.5 74870 77148 4800 0.5 131348 133626 1 73568 78451 1 130046 134928 table 8. ST7540 synthesized frequencies
ST7540 functional description 19/44 6.5 host processor interface ST7540 exchanges data with the host processor through a serial interface. the data transfer is managed by reg_data and rxtx lines, while data are exchanged using rxd, txd and clr/t lines. four are the ST7540 working modes: data reception data transmission control register read control register write reg_data and rxtx lines are level sensitive inputs. ST7540 features two type of host communication interfaces: spi uart the selection can be done through the uart/spi pin. if uart/spi pin is forced to ?0? spi interface is selected while if uart/spi pin is forced to ?1? uart interface is selected. the type of interface affects the data reception by setting the idle state of rxd line. when ST7540 is in receiving mode (reg_data=?0? and rxtx =?1?) and no data are available on mains (or rxd is forced to an idle state, i.e. with a conditioned detection method), the rxd line is forced to ?0? when uart/spi pin is forced to ?0? or it is forced to ?1? when uart/spi pin is forced to ?1?. the uart interface allows to connect an ua rt compatible device while spi interface allows to connect an spi compatible device. the allowed combinations of host interface/ST7540 mains access are: table 9. data and control register access bits configuration reg_data rxtx data transmission 0 0 data reception 0 1 control register read 1 1 control register write 1 0 table 10. host interface / ST7540 mains access combinations host device interface type uart/spi pin communication mode mains access asynchronous synchronous uart ?1? transmission x uart ?1? reception x spi ?0? transmission x spi ?0? reception x
functional description ST7540 20/44 figure 6. synchronous and asynchronous ST7540/host controller interfaces ST7540 allows to interface the host controlle r using a five line interface (rxd,txd,rxtx, clr/t, & reg_data) in case of synchronous mains access or using a 3 line interface (rxd,txd & rxtx) in asynchrono us mains access. since control register is not accessible in asynchronous mode, in this case reg_data pin must be tied to gnd. 6.5.1 communication bet ween host and ST7540 the host can achieve the mains access by selecting reg_data=?0? and the choice between data transmission or data reception is performed by selecting rxtx line (if rxtx =?1? ST7540 receives data from mains, if rxtx=?0? ST7540 transmits data over the mains). communication between host and ST7540 is different in asynchronous and synchronous mode: asynchronous mode: in asynchronous mode, data are exchanged without any data clock reference. the host controller has to recover the clock reference in receiving mode and control the bit time in transmission mode. if rxtx line is set to ?1? & reg_data=?0? (data reception), ST7540 enters in an idle state. after tcc time the modem starts providing received data on rxd line. if rxtx line is set to ?0? & reg_data=?0? (data transmission), ST7540 enters in an idle state and transmission circuitry is swit ched on. after tcc time the modem starts transmitting data present on txd line. rxd clr/t reg_data rxtx ST7540 host controller txd uart/asynchronous data interface rxd clr/t reg_data rxtx ST7540 host controller txd spi/synchronous data interface d03in1415
ST7540 functional description 21/44 synchronous mode: in synchronous mode ST7540 is always the master of the communication and provides the clock reference on clr/t line. when ST7540 is in receiving mode an internal pll recovers the clock reference. data on rxd line are stable on clr/t rising edge. when ST7540 is in transmitting mode the clock reference is internally generated and txd line is sampled on clr/t rising edge. if rxtx line is set to ?1? & reg_data=?0? (data reception), ST7540 enters in an idle state and clr/t line is forced low. after tcc time the modem starts providing received data on rxd line. if rxtx line is set to ?0? & reg_data=?0? (data transmission), ST7540 enters in an idle state and transmission circuitry is swit ched on. after tcc time the modem starts transmitting data present on txd line ( figure 8 ) . figure 7. receiving and transmitting data/recovered clock timing figure 8. data reception -> data transmission -> data reception transmitting bit synchronization clr/t rxd clr/t txd receiving bit synchronization t s t h d03in1416 t cc t ds t cr t cr t dh t s t h t b t cc clr_t rxd rxtx txd reg_data d03in1402
functional description ST7540 22/44 6.5.2 control register access the communication with ST7540 control register is always synchronous. the access is achieved using the same lines of the mains interface (rxd, txd, rxtx and clr/t) plus reg_data line. with reg_data = 1 and rxtx = 0, the data present on txd are loaded into the control register msb first. the ST7540 samples the txd line on clr/t rising edges. the control register content is updated at the end of the register access section (reg_data falling edge). in normal control register mode (control register bit 21 = ?0?, see ta bl e 1 2 ) if more than 24 bits are transferred to ST7540 only latest 24 bits are stored inside the control register. if less than 24 bits are transferred to ST7540 the control register writing is aborted. in order to avoid undesired control register writings caused by reg_data line fluctuations (for example because of surge or burst on mains), in extended control register mode (control register bit 21 = ?1? see ta b l e 1 2 ) exactly 24 or 48 bits must be transferred to ST7540 in order to properly write the control register, otherwise writing is aborted. if 24 bits are transferred, only the first 24 control register bits (from 23 to 0) are written. with reg_data = 1 and rxtx = 1, the content of the control register is sent on rxd port. the data on rxd are stable on clr/t rising edges msb first. in normal control register mode 24 bits are transferred from ST7540 to the host. in extended control register mode 24 or 48 bits are transferred from ST7540 to the host depending on content of control register bit 18 (with bit 18 = ?0? the first 24 bits are transferred, otherwise all 48 bits are transferred, see ta b l e 1 2 ). figure 9. data reception ? control register read ? data reception timing diagram figure 10. data reception ? control register write ? data reception timing diagram t cc t ds t dh t cr t cr t b t ds t dh t cc clr_t rxd reg_data rxtx d03in1404 bit23 bit22 t cc t cr t cr t cr t cr t b t dh t ds t cc clr_t rxd rxtx txd reg_data d03in1403 bit23 bit22 t s t h
ST7540 functional description 23/44 figure 11. data transmission ? control register read ? data reception timing diagram figure 12. data transmission ? control register write ? data reception timing diagram 6.6 receiving mode the receive section is active when rxtx pin =?1? and reg_data=0. the input signal is read on rx_in pin using sv ss as ground reference and then pre-filtered by a band pass filter (62khz max bandwidth at -3db). the pre-filter can be inserted setting one bit in the control register. the input stage features a wide dynamic range to receive signal with a very low signal to noise ratio. the amplitude of the applied waveform is automatically adapted by an automatic gain control block (agc) and then filtered by a narrow band band-pass filter centered around the selected channel frequency (14khz max at -3db). the resulting signal is down-converted by a mixer using a sinewave generated by the fsk modulator. finally an intermediate frequency band pass-filter (if filter) improves the signal to noise ration before sending the signal to the fsk demodulator. the fsk demodulator then send the signal to the rx logic for final digital filtering. digital filtering removes noise spikes far from the baud rate frequency and reduces the signal jitter. rxd line is forced to ?0? or ?1? (according the uart/spi pin level) when neither mark or space frequencies are detected on rx_in pin. mark and space frequency in receiving mode must be distant at least baudrate/2 to have a correct demodulation. while ST7540 is in receiving mode (rxtx pin =?1?), the transmit circuitry, power line interface included, is turned off. this allows the device to achieve a very low current consumption (5ma typ). t cc t ds t dh t cr t cr t cr t b t ds t dh t cc clr_t rxd txd reg_data rxtx d03in1405 bit23 bit22 t s t h t cc t ds t cr t cr t cr t dh t b t cc clr_t txd rxd reg_data rxtx d03in1401 bit23 bit22 t s t h t s t h
functional description ST7540 24/44 receiving sensitivity level selection it is possible to select the ST7540 receiving sensitivity le vel by control register (see ta bl e 1 2 ) or setting to ?1? the txd pin during reception phase (this condition overcomes the control register setting the sensitivity equal to bu threshold). increasing the device sensitivity allows to improve the communic ation reliability when the ST7540 sensitivity is the limiting factor. synchronization recovery system (pll) ST7540 embeds a clock recovery system to feature a synchronous data exchange with the host controller. the clock recovery system is realized by means of a second order pll. in synchronous mode, data on the data line (rxd) are stable on clr/t line rising edge (clr/t falling edge synchronized to rxd line transitions lock-in range). the pll lock-in and lock-out range is /2. when the pll is in the unlock condition rxd line is forced to ?0? or ?1? ac cording to the uart/spi pin level and clr/t is forced to ?0? only if the detection method ?preamble detection with conditioning? is selected.when pll is in unlock condition it is sensitive to rxd rising and falling edges. the maximum number of transition required to reach the lock-in condition is 5. when in lock-in condition the pll is sensit ive only to rxd rising edges to reduce the clr/t jitter. ST7540 pll is forced in the un-lock condition, when more than 32 equal symbols are received.due to the fact that the pll, in lock-in condition, is sensitive only to rxd rising edge, sequences equal or longer than 15 equal symbols can put the pll into the un-lock condition. figure 13. ST7540 pll lock-in range carrier/preamble detection the carrier/preamble block is a digital frequency detector circuit. it can be used to manage the mains access and to detect an incoming signal. two are the possible setting: ? carrier detection ? preamble detection clr/t rxd d03in1417 lock-in range
ST7540 functional description 25/44 carrier detection the carrier/preamble detection block notifies to the host controller the presence of a carrier when it detects on the rx_in input a signal with an harmonic component close to the programmed carrier frequency. the cd_pd signal sensitivity is identical to the data reception sensitivity (0.5mvrms typ. in normal sensitivity mode). when the device sensitivity is set by the txd line (sensitivity level equal to bu threshold) the cd_pd signal is conditioned to the bu signal. the cd_pd line is forced to a logic le vel low when a carrier is detected. preamble detection the carrier/preamble detection block notifies to the host controller the presence of a carrier modulated at the programmed baud rate for at least 4 consecutive symbols (?1010? or ?0101? are the symbols sequences detected). cd_pd line is forced low till a carrier signal is detected and pll is in the lock-in range. to reinforce the effectiveness of the information given by cd_pd block, a digital filtering is applied on carrier or preamble notification signal (see section 6.8: control register ). the detection time bits in the control register define the filter performance. increasing the detection time reduced the fals e notifications caused by noise on main line. the digital filter adds a delay to cd_pd notification equal to the programmed detection time. when the carrier frequency disappears, cd_pd line is held low for a period equal to the detection time and then forced high. during this time, some spurious data caused by noise can be demodulated and sent over rxd line. header recognition in control register extended mode (control register bit 21=?1?, see ta b l e 1 2 ) the cd_pd line can be used to recognize if an header has been sent during the transmission. with header recognition function enable (control register bit 18=?1?, see ta b l e 1 2 ), cd_pd line is forced low when a frame header is detected. if frame length count function is enabled, cd_pd is held low and a number of 16 bit word equal to the frame length selected is sent to the host controller. in this case, clr/t is forced to ?0? and rxd is forced to ?0? or ?1? (according the uart/spi pin level) when header has not been detected or after the frame length has been reached. if frame length count function is disabled, an header recognition is signaled by forcing cd_pd low for one period of clr/t line. in this case, clr/t and rxd signal are always present, even if no header has been recognized.
functional description ST7540 26/44 figure 14. cd_pd timing during rx figure 15. receiving path block diagram 6.7 transmission mode the transmission mode is set when rxtx pin =?0? and reg_data pin =?0?. in transmitting mode the fsk modulator and the power line interface are turned on. the transmit data (txd) enter synchronously or asynchronously to the fsk modulator. synchronous mains access: on clr/t rising edge, txd line value is read and sent to the fsk modulator. ST7540 manages the transmission timing according to the baudrate selected asynchronous mains access: txd data enter directly to the fsk modulator.the host controller manages the transmission timing in both conditions no protocol bits are added by ST7540. the fsk frequencies are synthesiz ed in the fsk modulator from a 16 mhz crystal oscillator by direct digital synthesis technique. the frequencies table in different configuration is reported in ta b l e 8 . the frequencies precision is same as external crystal one?s. t dcd t cd cd_pd rx_in d03in141 8 t dcd t cd rxd (uart/spi="1") demodulation active on rxd pin rxd (uart/spi="0") noise demodulated noise demodulated *' ' ! ' '

+ , '- , '.'! , '-!/'0/ , '.! , '1!. , '!-'0'
, ' , /

2 , '3!'0 /!/4
ST7540 functional description 27/44 in the analog domain, the signal is filtered in order to reduce the output signal spectrum and to reduce the harmonic distortion. the transition between a symbol and the following is done at the end of the on-going half fsk sinewave cycle. figure 16. transmitting path block diagram automatic level control (alc) the automatic level control block (alc) is a variable gain amplifie r (with 32 non linear discrete steps) controlled by two analog feed backs acting at the same time. the alc gain range is 0db to 30 db and the gain change is clocked at 5khz. each step increases or reduces the voltage of 1db (typ). two are the control loops acting to define the alc gain: ? a voltage control loop ? a current control loop the voltage control loop acts to keep the peak-to-peak voltage constant on vsense. the gain adjustment is related to the result of a peak detection between the voltage waveform on vsense and two internal voltage references. it is possible to protect the voltage control loop against noise by freezing the output level (see section 7.5: output voltage level freeze ). ? if vsense < vsense th - vsense hyst the next gain level is increased by 1 step ?if vsense th - vsense hyst < vsense < vsense th + vsense hyst no gain change ? if vsense > vsense th + vsense hyst the next gain level is decreased by 1 step !5
/ + 3 6 1

' / -
!
, '/ , '.!+ , '.! , '4!3 ' 3 "
functional description ST7540 28/44 the current control loop acts to limit the maximum peak output current inside pa _ o u t. the current control loop acts through the voltage control loop decreasing the output peak-to-peak amplitude to reduce the current inside the power line interface. the current sensing is done by mirroring the current in the high side mos of the power amplifier (not dissipating current sensing). the output current limit (up to 500mrms), is set by means of an external resistor (r cl ) connected between cl and v ss . the resistor converts the current sensed into a voltage signal. the peak current sensing block works as the output voltage sensing block: ?if v(cl) < cl th - cl hyst voltage control loop acting ?if cl th - cl hyst < v(cl) < cl th + cl hyst no gain change ?if v(cl) > cl th + cl hyst the next gain level is decreased by 1 step figure 17 shows the typical connection of current anvoltage control loops. figure 17. voltage and current feedback external interconnection example voltage control loop formula r1 alc voltage loop current loop vsense cl pa_out/tx_out vout pk vsense hyst vsense th 1.865v (typ) v cl hyst v cl th avss 10nf r2 rcl vout 80pf typ. d03in1421 v outpk r 1 r 2 + r 2 -------------------- vsense th vsense hyst () ? ?
ST7540 functional description 29/44 note: notes: the rate of r2 takes in account the input resistance on the v sense pin (36k ? ). 10nf capacitor effect has been neglected. figure 18. typical output current vs rcl integrated power line interface (pli) the power amplifier (pa) is a cmos ab class power amplifier. the pa requires, to ensure a proper operation, a regulated and well filtered supply voltage. vcc voltage and pa_out voltage must fulfil the following formulas to work without clipping phenomena: table 11. v out vs. r1 & r2 resistors value vout (vrms) vout (db v) (r1+r2)/r2 r2 (k ? ) r1 (k ? ) 0.150 103.5 1.1 7.5 1.0 0.250 108.0 1.9 5.1 3.9 0.350 110.9 2.7 3.6 5.6 0.500 114.0 3.7 3.3 8.2 0.625 115.9 4.7 3.3 11.0 0.750 117.5 5.8 2.7 12.0 0.875 118.8 6.6 2.0 11.0 1.000 120.0 7.6 1.6 10.0 1.250 121.9 9.5 1.6 13.0 1.500 123.5 10.8 1.6 15.0 irms (ma) rcl(k ? ) d01in1311 120 220 320 420 520 620 720 820 920 1020 1120 1220 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 v cc vpaout ac () 2 --------------------------------------- - vpout dc () 3v ++ vpout dc () vpaout ac () 2 --------------------------------------- - 1.5v ?
functional description ST7540 30/44 inputs and outputs of pa are available on pins pa_in-,pa_in+ and pa_out. user can easily select an appropriate active filtering topology to filter the signal present on tx_out pin. tx_out output has a current capa bility much lower than pa_out. figure 19. pa_out and v cc relationship v cc v pa_out(ac) d03in1425 3v v t v ss 1.5v v pa_out(dc)
ST7540 functional description 31/44 figure 20. power line interface topology figure 21. power line interface startup timing diagram r1 alc voltage loop current loop vsense cl r2 rcl 80pf typ. tx_out d03in1422 vcc r3 r4 vss pa_out - + pa_in+ pa_in- z1 z2 ac line t st 2.1v 0v t alc t rxtx rxtx tx_out step number 16 17 18 31 d03in1408
functional description ST7540 32/44 6.8 control register the ST7540 is a multi-channel and multifunction transceiver. an internal 24 or 48 bits (in extended mode) control register allows to manage all the programmable parameters ( ta bl e 1 2 ). the programmable functions are: channel frequency baud rate deviation watchdog transmission timeout frequency detection time detection method mains interfacing mode output clock sensitivity mode input pre-filter in addition to these functions the extended mode provides 24 additional bits and others functions: output level freeze frame header recognizes (one 16 bits header of or two 8 bits headers) with support to frame length bit count
ST7540 functional description 33/44 table 12. control register functions function value selection note default 0 to 2 frequencies bit2 bit1 bit0 60 khz 66 khz 72 khz 76 khz 82.05 khz 86 khz 110 khz 132.5 khz 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 132.5 khz 3 to 4 baud rate bit 4 bit 3 600 1,200 2,400 4,800 0 0 1 1 0 1 0 1 2400 5deviation bit 5 0.5 1 0 1 0.5 6 watchdog bit 6 disabled enabled (1.5 s) 0 1 enabled 7 to 8 transmission time out bit 8 bit 7 disabled 1 s 3 s not used 0 0 1 1 0 1 0 1 1 sec 9 to 10 frequency detection time bit 10 bit 9 500 s 1 ms 3 ms 5 ms 0 0 1 1 0 1 0 1 1 ms 11 reserved do not force a different value 0
functional description ST7540 34/44 function value selection note default bit 13 bit 12 12 to 13 detection method preamble detection without conditioning 00 preamble detection notification on cd_pd line clr/t and rxd signal always present in uart mode (uart/spi pin set to 1) this configuration is not allowed. carrier detection without conditioning preamble detection with conditioning 01 preamble detection notification on cd_pd line. clr/t and rxd line are forced to "0" when preamble has not been detected or pll is in unlock condition. in uart mode (uart/spi pin set to 1) this configuration is not allowed. carrier detection without conditioning 10 carrier detection notification on cd_pd line clr/t and rxd signal always present carrier detection with conditioning 11 carrier detection notification on cd_pd line clr/t line is forced to ?0? and rxd line is forced to ?0? or ?1? (according the uart/spi pin level) when carrier is not detected bit 14 14 mains interfacing mode synchronous asynchronous 0 1 asynchronous bit 16 bit 15 15 to 16 output clock 16 mhz 8 mhz 4 mhz clock off 0 0 1 1 0 1 0 1 4 mhz bit 17 active only if extended control register is enable (bit 21=?1?) 17 output voltage level freeze enabled disabled 0 1 disabled bit 18 active only if extended control register is enable (bit 21=?1?) 18 header recognition disabled enabled 0 1 disabled bit 19 active only if header recognition function (bit 18=?1?) and extended control register (bit 21=?1?) are enable 19 frame length count disabled enabled 0 1 disabled table 12. control register functions
ST7540 functional description 35/44 function value selection note default bit 20 active only if extended control register is enable (bit 21=?1?) 20 header length 8 bits 16 bits 0 1 16 bits bit 21 extended register enables functions on bit 17, 18,19 and 20 21 extended register disable (24 bits) enabled (48 bits) 0 1 disabled (24 bits) bit 22 22 sensitivity mode normal sensitivity high sensitivity 0 1 normal bit 23 23 input filter disabled enabled 0 1 disabled 24 to 39 frame header from 0000h to ffffh one 16 bits header or two 8 bits headers (msb first) depending on bit 20 9b58h 40 to 47 frame length from 01h to ffh number of 16 bits words expected 08h table 12. control register functions
auxiliary analog and digital functions ST7540 36/44 7 auxiliary analog and digital functions 7.1 band in use the band in use block has a carrier detection like function but with a different input sensitivity (83.5 db v typ.) and with a different bandpa ss filter selectiv ity (40db/dec). bu/therm line is forced high when a signal in band is detected. to prevent bu/therm line false transition, band in use signal is conditioned to carrier detection internal signal. this function is en abled only in receiving mode (in transmission mode the bu/therm pin is used for thermal shutdown signaling, see section 7.8: thermal shutdown ). 7.2 time out time out function is a protection against a too long data transmission. when time out function is enabled after 1 or 3 second of continuos transmission the transceiver is forced in receiving mode. this function allows ST7540 to automatically manage the cenelec medium access specification. when a time-out event occur, the transmission section is disabled for at least 125 ms. to unlock the time out condition rxtx should be forced high. during the time out period only register access or reception mode are enabled. during reset sequence if rxtx line =?0? & re g_data line =?0?, time out protection is suddenly enabled and ST7540 must be configured in data reception after the reset event before starting a new data transmission. time out time is programmable using control register bits 7 and 8 ( ta bl e 1 2 ). figure 22. time-out timing and unlock sequence ,7'8 '98 ,

ST7540 auxiliary analog and digital functions 37/44 7.3 reset & watchdog rsto output is a reset generator for the application circuitry. during the ST7540 startup sequence is forced low. rsto becomes high after a t rsto delay from the end of oscillator startup sequence. inside ST7540 is also embedded a watchdog function. the watchdog function is used to detect the occurrence of a software fault of the host controller. the watchdog circuitry generates an internal and external reset (rsto low for t rsto time) on expiry of the internal watchdog timer. the watchdog timer reset can be achieved applying a negative pulse on wd pin (see figure 23 ). figure 23. reset and watchdog timing 7.4 output clock mclk is the master clock output. the clock frequency sourced can be programmed through the control register to be a ratio of the crystal oscillator frequency (fosc, fosc/2 fosc/4). the transition between one frequency and another is done only at the end of the ongoing cycle. the oscillator can be disabled usin g control register bits 15 and 16 ( ta bl e 1 2 ). 7.5 output voltage level freeze the output level freeze function, when enabled, turns off the voltage control loop once the alc stays in a stable condition for about 3 periods of control loop, and maintains a constant gain until the end of transmission. output level freeze can be enabled using control register bit 17 ( ta bl e 1 2 ). this function is available only using the extended control register (control register bit 21=?1?). 7.6 extended control register when extended control register function is enabled, all the 48 bits of control register are programmable. otherwise, only the first 24 bits of control register are programmable. the functions header recognition, frame bit count and output voltage freeze are available only if extended control register function is enabled. extended control register can be enabled using control register bit 21( ta b l e 1 2 ). t wo t rsto t wd t wm t rsto rsto wd d03in1410
auxiliary analog and digital functions ST7540 38/44 7.7 under voltage lock out the uvlo function turns off the device if the v cc voltage falls under 4v. hysteresis is 340mv typically. 7.8 thermal shutdown the ST7540 is provided of a thermal protection which turn off the pli when the junction temperature exceeds 170c 10% . hysteresis is around 30c. when shutdown threshold is overcome, pli interface is switched off. thermal shutdown event is notified to the host controller using bu/therm line. when bu/therm line is high, ST7540 junction temperature exceed the shutdown threshold (not latched). this function is enabled only in transmission mode (in receiving mode the bu/therm pin is used for band in use signaling, see band in use function section 7.1: band in use ). 7.9 5v voltage regulator ST7540 has an embedded 5v linear regulator externally available (on pin vdc) to supply the application circuitry. the 5v linear regulator has a very low quiescent current (50 a) and a current capability of 50ma. the regulator is protected against short circuitry events. 7.10 3.3v voltage regulator the v dd pin can act either as 3.3v voltage output or as input digital supply. when the v dd pin is externally forced to 5v all the digital i/os operate at 5v, otherwise all the digital i/os are internally supplied at 3.3v. the v dd pin can also source 3.3v voltage to supply external components. the 3.3v linear regulator has a very low quiescent current (50 a) and a current capability of 50ma. the regulator is protected again st short circuitry events. 7.11 power-up procedure to ensure ST7540 proper power-up sequence, v cc and v dd supply has to fulfil the following rules: 1. v cc rising slope must not exceed 100v/ms. 2. when v dd is below 5v/3.3v: v cc -v dd < 1.2v. when v dd supply is connected to vdc (5v digital supply) the above mentioned relation can be ignored if vdc load < 50ma and if the filtering capacitor on vdc < 100uf. if v dd is not forced to 5v, the digital i/os are internally supplied at 3.3 v and if v dd load < 50ma and the filtering capacitor on v dd < 100uf the second relation can be ignored .
ST7540 auxiliary analog and digital functions 39/44 figure 24. power-up sequence voltage time 5v/3.3v v cc -v dd v cc v dd d03in1424
auxiliary analog and digital functions ST7540 40/44 figure 25. application schematic ex ample with coupling transformer. ST7540 wd rxd rxtx reg/data txd clr/t cd/pd bu/therm mclk rsto pa_out v cc 15 17 x2 22 x1_oscin 21 vsense cl 16 24 tx_out 19 23 28 test2 27 test1 rx_in 25 9 v dd 26 vdc 13 1 4 5 6 8 7 10 11 2 gnd 3 svss 20 host controller ac line ac/dc converter no external components for power line driver single suppy 5v supply for host controller clock & reset for host controller 5 lines serial interface voltage regulation & current protection r1 r2 rcl c1 d03in1412a 12 uart/spi v ss pa_in+ 18 pa_in- 14 z1 z2 r3 r4
ST7540 mechanical data 41/44 8 mechanical data in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect . the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com
mechanical data ST7540 42/44 table 13. htssop28 mechanical data dim. mm. inch min. typ. max. min. typ. max. a 1.2 0.047 a1 0.15 0.006 a2 0.8 1.0 1.05 0.031 0.039 0.041 b 0.19 0.3 0.007 0.012 c 0.09 0.2 0.003 0.008 d (*) 9.6 9.7 9.8 0.377 0.382 0.385 d1 3.3 0.130 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 (*) 4.3 4.4 4.5 0.169 0.173 0.177 e2 1.5 e 0.65 0.026 l 0.45 0.6 0.75 0.018 0.024 0.029 l1 1.0 0.039 k 0 (min), 8 (max) aaa 0.1 0.004 figure 26. package dimensions
ST7540 revision history 43/44 9 revision history table 14. revision history date revision changes 15-mar-2006 1 initial release. 25-sep-2006 2 updated electrical characteristics and power amplifier description
ST7540 44/44 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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